1. Technical Field
This invention relates generally to electronic devices, and more particularly, to resistive memory devices.
2. Background Art
FIG. 1 illustrates a two-terminal metal-insulator-metal (MIM) resistive memory device 30. The memory device 30 is typically formed in an opening in a layer of insulating material 31 such as silicon dioxide or silicon nitride. The device includes a metal, for example copper, Cu electrode 32, an active layer 34 of for example CuxO on and in contact with the electrode 32, and a metal, for example nickel, Ni electrode 36 on and in contact with the layer 34, with the electrodes and layer in contact with the material of the layer. As an example of the operational characteristics of such a device 30, with reference to FIG. 2, initially, assuming that the memory device 30 is unprogrammed, in order to program the memory device 30, an electrical potential Vpg (the “programming” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. Upon removal of such potential the memory device 30 remains in a conductive or low-resistance state having an ON-state resistance.
In the read step of the memory device 30 in its programmed (conductive) state, an electrical potential Vr (the “read” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. This electrical potential is less than the electrical potential Vpg applied across the memory device 30 for programming (see above). In this situation, the memory device 30 will readily conduct current, which indicates that the memory device 30 is in its programmed state.
In order to erase the memory device 30, an electrical potential Ver (the “erase” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction of from electrode 32 to electrode 36. (The programming and erasing described above are provided as an example. As another example, the program and erase operations may employ the same bias polarity).
In the read step of the memory device 30 in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32 as described above. With the active layer 34 (and memory device 30) in a high-resistance or substantially non-conductive OFF state, the memory device 30 will not conduct significant current, which indicates that the memory device 30 is in its erased state.
While such a memory device is effective in operation, it will be understood that improvements in performance, such as improved switching speed and lower power usage, are always desirable. Therefore, what is needed is a memory device which exhibits improved switching speed along with lower power usage.